1. Field of the Invention
This invention relates to electronic circuits, and more particularly, to clock circuits.
2. Description of the Related Art
Clock dividers are commonly used in synchronous circuits. Generally speaking, a clock divider may be a circuit that receives a first clock signal at a first frequency and outputs a second clock signal at a second frequency lower than the first. The lower frequency of the second clock signal may be obtained by “dividing” the first clock signal by a specified divisor. For example, a clock divider may receive a first clock signal having a frequency of 100 MHz, and output a second clock signal having a frequency of 50 MHz. Accordingly, the second clock signal may be obtained by dividing the frequency of the first clock signal by a divisor of two in this example.
Some clock dividers may be configured to divide the frequency of an input clock signal by an even divisor (e.g., 2, 4, 6, etc.). Other clock dividers may be configured to divide the frequency of a clock signal by an odd divisor (e.g., 3, 5, 7, etc.). Furthermore, some clock dividers may be programmable in that the divisor may be selectable and changeable during operation. Clock dividers that are programmable and that may divide the frequency of an input clock signal by either an even or odd divisor may also be implemented. Such a clock divider may be obtained by providing completely separate odd and even clock divider circuits and selecting the even clock divider or the odd clock divider based on the divisor.